1. Field of the Invention
The embodiments discussed herein are related to a semiconductor device and a method of manufacturing a semiconductor device.
2. Description of the Related Art
Insulated gate bipolar transistors (IGBTs) having breakdown voltage ratings of 400V, 600V, 1200V, 1700V, 3300V, or higher and used for semiconductor devices in power semiconductor devices are commonly known. IGBTs are used in power converting equipment such as converters and inverters. Low loss, high efficiency, high breakdown voltage, and low noise are demanded of such power semiconductor devices. Measures for electro-magnetic compatibility (EMC) are particularly important.
EMC is dependent on the rate of voltage change over time (dV/dt) and during inverter operation, the dV/dt of a free-wheeling diode ((FWD) (opposing arm)) in a low current region at turn-on of an IGBT (reverse recovery of the FWD (the opposing arm)) is most likely to increase. Therefore, dV/dt has to be reduced to a reasonable value by increasing the gate resistance Rg of the IGBT and reducing the turn-on speed. Thus, improvement of dV/dt controllability at IGBT turn-on (hereinafter, turn-on dV/dt controllability) by gate resistance Rg is important.
A structure of an active region for IGBT current driving will be described taking a typical trench gate-type IGBT as an example. The active region is a region in which current flows during an ON state. FIG. 15 is a cross-sectional view of a structure of a conventional trench gate-type IGBT. As depicted in FIG. 15, in the active region, a trench gate-type metal oxide semiconductor (MOS) insulated gate is disposed on a front surface side of an n−-type semiconductor substrate becoming an n−-type drift layer 101. In particular, on the front surface side of the n−-type semiconductor substrate, a trench (hereinafter, gate trench) 102 is disposed so as to divide a surface layer of the n−-type drift layer 101. A gate electrode 104 is disposed inside the gate trench 102, via a gate insulating film 103.
At a mesa region of n−-type drift layer 101, separated by adjacent gate trenches 102, a p-type base region 105 is disposed. An n+-type emitter region 106 and a p+-type contact region 107 are selectively disposed in the p-type base region 105, in a surface layer of a substrate front surface side of the p-type base region 105. An emitter electrode 108 contacts the n+-type emitter region 106 and the p+-type contact region 107 through a contact hole penetrating, in a depth direction, an interlayer insulating film 109 disposed on a substrate front surface, and is electrically isolated from the gate electrode 104 by the interlayer insulating film 109. In a mesa region where the n+-type emitter region 106 is not disposed, a p+-type region (hereinafter, floating p+-type region) 110 electrically isolated from the emitter electrode 108 by the interlayer insulating film 109 is disposed to secure breakdown voltage.
An n-type field stop (FS) layer 111 and a p+-type collector layer 112 are disposed in a back side of the n−-type semiconductor substrate. A collector electrode 113 contacts a p+-type collector layer 112. In a trench gate-type IGBT of such a conventional structure, hole current flows in the floating p+-type region 110 at turn-on, whereby the electric potential of the floating p+-type region 110 increases and displacement current arising from this electric potential increase flows to the gate electrode 104. As a result, the turn-on speed for the interval related to dV/dt is determined and therefore, turn-on dV/dt controllability degrades (for example, refer to Tokura, N., “Influence of Floating P-Base on Turn-On Characteristics of Trench-Gate FS-IGBT”, The Institute of Electrical Engineers Journal D, The Institute of Electrical Engineers of Japan (IEEJ), 2010, Vol. 130, NO. 6, pp. 728-733; and Onozawa, Y., et al, “Development of the next generation 1200V trench-gate FS-IGBT featuring lower EMI noise and lower switching loss”, Proceedings of the 19th International Symposium on Power Semiconductor Devices & ICs, (Jejudo), May 27 to 30, 2007, pp. 13-16).
The following device has been proposed as a device that improves turn-on dV/dt controllability by the gate resistance Rg. A first groove and a second groove are formed so as penetrate a p base layer and n layer, and reach an upper layer portion of an n− layer. The first groove is adjacent to an n+ emitter region and inside the first groove, a gate electrode is formed. A polysilicon region is formed inside the second groove. The second groove differs from the first groove in that the n+ emitter region is not formed in a neighboring region, and a gate electrode is not formed inside the second groove (for example, refer to Japanese Patent Application Laid-Open Publication No. 2002-353456). Japanese Patent Application Laid-Open Publication No. 2002-353456 adopts a dummy gate structure where a polysilicon region of an emitter electric potential is disposed inside the second groove via an insulating film, whereby holes accumulated in the p base layer pass to the emitter electrode during OFF operation, improving OFF operation characteristics.
A structure of the active region of a trench gate-type IGBT that includes a dummy gate structure will be described. FIG. 16 is a cross-sectional view of another example of a structure of a conventional trench gate-type IGBT. A trench gate-type IGBT having a dummy gate structure depicted in FIG. 16, similar to the typical trench gate-type IGBT depicted in FIG. 15, has a trench gate-type MOS gate structure. Further, a trench (hereinafter, emitter trench) 122 is disposed so as to be adjacent to a trench (gate trench) 102 configuring the MOS gate structure, sandwiching the p-type base region 105 in between. An electrode (dummy gate electrode) 124 of the emitter electric potential is disposed inside the emitter trench 122 via an insulating film (dummy gate insulating film) 123.
Configuration of the trench gate-type IGBT having the dummy gate structure is similar to that of the typical trench gate-type IGBT depicted in FIG. 15 with the exception of the emitter trench 122, the dummy gate insulating film 123, and the dummy gate electrode 124. In the trench gate-type IGBT having the dummy gate structure, in particular, during high voltage such as at turn-on initially, holes accumulate along the emitter trench 122, forming a current path of low resistance through which hole current flows from the floating p+-type region 110 to the emitter electrode 108. Therefore, increased electric potential in the floating p+-type region 110 may be suppressed, improving turn-on dV/dt controllability by the gate resistance Rg to a greater extent than with a typical trench gate-type IGBT.
Further, as another trench gate-type IGBT, a device has been proposed in which a gate electrode inside a trench extends onto a substrate front surface, providing a gate electrode of a floating p+-type region on an entire surface of a substrate front surface side, via an insulating film (for example, refer to U.S. Pat. No. 6,815,769 (FIGS. 11 and 12), Japanese Patent Application Laid-Open Publication No. 2005-191221 (FIG. 9), and Japanese Patent Application Laid-Open Publication No. H5-243561 (paragraph 0099, FIGS. 85, 87, 91, 93)).